 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 82510 sy / d0308 ms 20081010-s00002 no.a1345-1/36 LC07410LG overview the LC07410LG is an ic that integrates a video driver with audio codec developed for digital still cameras and other portable equipment. incorporating 16-bit a/d and d/a converters as well as a microphone amp lifier and speaker driver that are necessary for audio recording and playback, the one-chip ic is ideal for use to create audio interfaces. functions ? audio block ? ? method 16-bit monaural a/d and d/a converters ? generates bias voltage (2.3v) for microphone ? supports microphone amplifier differential inputs (0/+20/+26db) ? amplifier with automatic level control (alc) (-14db to +34db) for recording system ? wind cut hpf ? two programmable digital filter hsf/notch filter/lpf/eq ? digital volume with automatic level control (alc) for playback system supports zerocross detection and soft switching ? line output on-chip mute and pop-noise suppression circuits ? speaker driver supports v dd s = 5v (piezoelectric speaker supported) btl drive, rated output of 350mw at 8 , v dd s = 3v 1w at 8 , v dd s = 5v idling current adjustable supports beep input, volume level switchable ? audio interfaces i 2 s, left-justified mode, right-justified mode ? pll input: 12mhz, 13.5mhz, 24mhz, 27mhz sampling frequency: 7.86khz to 48khz pll master mode/slave (ext) mode ? loopback: adout to dain switch incorporated ? video block ? dc direct coupling input/output ? built-in 6th order low-pass filter (fc = 7.5mhz) ? amplifier gain selectable (6db or 12db) ? drive capacity 75 , 1 system continued on next page. orderin g numbe r : ena1345a cmos ic monaural codec + audio i/f + video driver
LC07410LG no.a1345-2/36 continued from preceding page. ? reg block ? 3.0v output linear regulator for audio block ? overcurrent protective function (typ: 200ma) ? quick discharge activity ? 3-line serial register control ? digital i/o 1.8v supported ? supply voltage v dd io = 1.8v/3.3v (1.71 to 3.6v) v dd a = v dd p =3 .0v (2.7 to 3.6v) v dd r = 3.3v (3.2 to 3.6v) v dd v = dv dd = 3.3v (2.7 to 3.6v) v dd s = 3.3/5v (2.7 to 5.5v) ? operating ambient temperature: -20 to +80 c function comparison table of lc07410 and lc074146 function lc07410 lc074146 logic i/o 1.8v accepted { 3v regulator { beep sound generator { pll frequencies flexible pre-fix ext-beep gain 0db, -15/-18/-21db -12/-15/-18/-21db alc attack speed 2step variable monotonic alc recovery speed 3step variable monotonic alc noise gate function { digital filters wind cut hpf +2 programmable filters wind cut hpf + eq (hsf) + notch specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage (5v system) v dd 5 max v dd s -0.3 to 7.0 v maximum supply voltage (3v system) v dd 3 max other than v dd s -0.3 to 4.0 v input voltage v in max -0.3 to 4.0 v output voltage v out max -0.3 to 4.0 v input/output voltage v io max -0.3 to 4.0 v v dd srange v dd s 2.7 to 5.5 v v dd rrange v dd r 3.2 to 3.6 v v dd arange v dd a, v dd p, v dd v, dv dd 2.7 to 3.6 v allowable operating voltage range v dd iorange v dd io 1.71 to 3.6 v allowable power dissipation pd max ta = 80 c * 500 mw operating ambient temperature topr -20 to +80 c storage ambient temperature tstg -55 to +125 c * mounted on a specified board: 40mm 50mm 0.8mm, glass epoxy board 2s2p (4-layer board) LC07410LG no.a1345-3/36 recommended operating range at ta = 25 c, v ss v = dv ss = v ss r = v ss a = 0v ratings parameter symbol conditions min typ max unit v dd io v dd io pin 1.71 3.3 3.6 v dv dd dv dd pin 2.7 3.3 3.6 v v dd ana v dd p, v dd a pin 2.7 3.0 3.6 v v dd v v dd v pin 2.7 3.3 3.6 v v dd r v dd r 3.2 3.3 3.6 v supply voltage v dd s v dd s pin 2.7 3.3/5.0 5.5 v v dd dv dv dd -v dd v 0.3 v v dd dr dv dd -v dd r 0.3 v v dd id v dd io-dv dd 0.3 v v dd pr v dd p-v dd r 0.3 v v dd pa v dd p-v dd a 0.3 v v dd as v dd a-v dd s 0.3 v supply voltage gap v dd vs v dd v-v dd s 0.3 v inpupt high level voltage v ih (*1) 0.8 v dd io v dd io v input low level voltage v il (*1) dv ss 0.2 v dd io v input clock frequency fmclk mclkin pin 2.012 27 mhz input clock duty dutymclk mclkin pin 0.45 0.50 0.55 % (*1) applicable pins: pdnb, csb, sck, sda, te stin, dain, mclkin, bclk , lrlk (in input mode) electrical characteristics at ta = 25 2 c, v dd io = 1.71 to 3.6v, v dd a = v dd p = v dd v = dv dd = 2.7 to 3.6v, v dd r = 3.2 to 3.6v, v ss s = 2.7 to 5.5v, v ss v = dv ss = v ss r = v ss a = 0v ratings parameter symbol conditions min typ max unit input high level current i ih v i = v dd io (*1) +1 a inputp low level current i il v i = dv ss (*1) -1 a output high level voltage v oh 1 i oh = -1ma (*2) 0.8 v dd io v output low level voltage v ol 1 i ol = 1ma (*2) 0.2 v dd io v (*1) applicable pins: pdnb, csb, sck, sda, te stin, dain, mclkin, bclk, lrck (in input mode) (*2) applicable pins: adout, bclk, lrck (in output mode) analog characteristics at ta = 25 c, v dd a = v dd p = 3.0v, v dd io = dv dd = v dd s = v dd v = v dd r = 3.3v, fs=48khz ratings parameter symbol conditions min typ max unit current drain rec time i dd ra1 reg/pll/mic/pga/adc on, no input signal 9.0 13.8 18.0 ma pb (line) time i dd pa2 reg/pll/dac/line on, no input signal 8.0 12.2 16.0 ma pb (spk) time i dd pa3 reg/pll/dac/spk on, no input signal 11.0 15.2 21.0 ma video block 1 i dd v1 v dd v, no input signal 4.0 6.1 8.0 ma video block 2 i dd v2 v dd v, video in = white 50% 8.0 12.8 16.0 ma power down time current i dd pd v dd a+v dd p+v dd r+v dd s+v dd v+dv dd +v dd io, clock stopped 1.0 10 a mic v in = -30dbv, 1khz, mgain[1:0] = 01 -1 0 1 db v in = -30dbv, 1khz, mgain[1:0] = 10 19 20 21 db mic amplifier gain v g mic v in = -30dbv, 1khz, mgain[1:0] = 11 25 26 27 mic amplifier output thd+n thdnmic v in = -30dbv, 1khz, mgain[1:0] = 11 -80 -70 db mic amplifier output noise voltage v no mic mic in no signal, a-weight ed, mgain[1:0] = 11 -88 -82 dbv mic bias output voltage vmicpwr r l = 5k 2.2 2.3 2.4 v continued on next page. LC07410LG no.a1345-4/36 continued from preceding page. ratings parameter symbol conditions min typ max unit alc gain change dgalc 1 db gain control range vgalc -14 +34 db adc: alcin input, alcoff, pga gain = 0db analog input voltage vinad 0dbfs, 1khz 0.6 v dd a vp-p thd+n thdnad -1dbfs, 1khz -80 -74 db dynamic range drad -60dbfs, a-weighted 80 86 db s/n ratio snad alcin no signal, a-weighted 80 86 db dac dgvol1 +12db to -10db 0.5 db dgvol2 -11db to -42db 1 db digital volume change dgvol3 -44db to -64db 2 db line: dac line gain = 0db, dvol = 0db analog output voltage v outda 0dbfs, 1khz 0.6 v dd a vp-p thd+n thdnda 0dbfs, 1khz -83 -74 db dynamic range drda -60dbfs, a-weighted 80 88 db s/n ratio snda a-weighted 80 88 db spk spk amplifier gain vgsp spkin = -9dbv, 1khz , btl, r l = 8 11 12 13 db spk output distortion hdsp spki n = -9dbv, 1khz 0.2 1 % spk output noise voltage vnosp spkin no signal, r l = 8 -86 -80 dbv spk maximum rated output vomsp r l = 8 , thd = 3% 300 350 mw btl, r l =8 bpvol[1:0] = 00 -2 0 2 db btl, r l = 8 bpvol[1:0] = 01 -16 -15 -14 db btl, r l = 8 bpvol[1:0] = 10 -19 -18 -17 db beep gain vgbp btl, r l = 8 bpvol[1:0] = 11 -22 -21 -20 db regulator regulator output voltage v o reg i out = 20ma 2.9 3.0 3.1 v video driver vgain[1:0] = 00, vdin = 1vp-p 100% white 5 6 7 db video amplifier gain v g video vgain[1:0] = 10, vdin = 0.5vp-p 100% white 11 12 13 db f = 8mhz/100khz -4.5 0 db frequency characteristics fva f = 20mhz/100khz -40 -35 db input impedance rvin 100 120 k adc filter characteristics ratings parameter conditions min typ max unit remarks resolution 16 bit passband 0.045db 0 0.4535fs 21.8khz@fs = 48khz stopband 0.5465fs 26.2khz@fs = 48khz passband ripple 0 to 20khz 0.045 db stopband attenuation -69 db output data delay 58 1/fs hpf cutoff frequency -3db 0.0000385fs hz 1.85hz@fs = 48khz LC07410LG no.a1345-5/36 dac filter characteristics ratings parameter conditions min typ max unit remarks resolution 16 bit passband 0.015db 0 0.4535fs 21.8khz@fs = 48khz stopband 0.5465fs 26.2khz@fs = 48khz passband ripple 0.015 db stopband attenuation -63 db output data delay 48 1/fs hpf cutoff frequency -3db 0.0000385fs hz 1.85hz@fs = 48khz switching characteristics ratings parameter symbol conditions min typ max unit pll pll used 12 27 mhz ckin frequency fcki ext input present 2.012 24.576 mhz fbclk = 0 64fs bclk frequency fbck fbclk = 1 32fs bclk duty cycle dtbk 45 50 55 % lrck frequency flr 7.86 48 khz lrck duty cycle dtlr 45 50 55 % clk transition time trck rise time, mclkin/bclk/lrck inputs present 10 ns clk transition time tfck fall time, mclkin/bclk/lrck inputs present 10 ns package dimensions unit : mm (typ) 3370 sanyo : flga40(4.4x3.6) 3.6 4.4 12345 678 fe dcba 0.45 0.55 0.5 0.85 max 0.0 nom 0.3 0.5 top view side view bottom view LC07410LG no.a1345-6/36 pin assignment nc adout v dd io dv ss sck nc mclkin lrck dv dd testin sda csb mclko dain pdnb vdref v dd r bclk v ss r regout vcofil v dd p v ss v vdout v dd v vdin alcin micpwr v dd a beep v ss s spoutp micout micinn lout2 v dd s spoutn nc lout1 spkin nc micinp vref v ss a abc def 8 7 6 5 4 3 2 1 top view block diagram vol micinp micinn mic amp micpwr mic power micout alcin 0/+20/+26db v dd a v ss a vref vref lout1 0/4/6/8db mute 0/6db lout2 spkin beep spk amp spoutn spoutp v dd s v ss s adc -14 to +34db dac alc ctl digital filter pll vcofil i/f mclkin mclko bclk lrck adout dain v dd io dv dd dv ss testin beep gen lpf vdin vdout v dd v +6/+12db ref vdref v ss v pdnb mode ctl sda sck csb ldo v dd p v ss r vreg v dd r 3.3v 3.0v line out 3.3v or li+ batt. 3.3v video out video dac 1.8v or 3.3v 1.8v or 3.3v 3.3v p/ dsp LC07410LG no.a1345-7/36 pin function (note) i/o: i => input, is => schmitt input , o => output, io s=> schmitt input/output pin no. pin name i/o function equivalent circuit b3 micpwr o microphone power supply output (2.3v) b1 micinp i microphone amplifier input (+ side) 70k b2 micinn i microphone amplifier input (- side) 70k c3 v dd a ? analog block power supply (3v) c1 vref o 3v analog power supply reference voltage output c2 v ss a ? analog block ground (0v) d1 lout1 o line output 1 d2 lout2 o line output 2 d3 beep i beep signal input, mixed to speaker amplifier e1 spkin i speaker amplifier input 5k e1 d3 5k 107k 10k 5k continued on next page. LC07410LG no.a1345-8/36 continued from preceding page. continued on next page. pin no. pin name i/o function equivalent circuit e2 v dd s ? speaker analog power supply f2 spoutn o speaker output (-) f3 spoutp o speaker output (+) e3 v ss s ? speaker analog ground e4 v dd v ? video driver analog power supply f4 vdin i video signal input 120k 120k f5 vdout o video signal output f6 vdref o video vref 500 50k 500 e5 v ss v ? video driver ground e6 pdnb is reset (negative polarity) f7 csb is chip select (negative polarity) microcontroller if e8 sck is serial clock microcontroller if e7 sda is serial data input microcontroller if schmitt d8 dv ss ? digital ground (0v) c7 dv dd ? digital power supply (3.3v) c8 v dd io ? digital i/o power supply (3.3v/1.8v) d7 testin i test input (v ss fixed in normal operation) d6 dain i dac serial data input b8 adout o adc serial data output LC07410LG no.a1345-9/36 continued from preceding page. pin no. pin name i/o function equivalent circuit b7 lrck ios lr clock input c6 bclk ios bit clock input schmitt a6 mclko o master clock output (default: set to low, serial setting enables output/addr: 16h) a7 mclkin i master clock input b6 v dd r ? regulator power supply input (3.3v) b5 regout o regulator output pin 144k 100k 100 a5 v ss r ? regulator block ground a4 vcofil o vco filter pin 100 b4 v dd p ? pll block supply (3.0v) a3 alcin i alc amplifier input 20k a2 micout o microphone amplifier output LC07410LG no.a1345-10/36 interface timing characteristics ratings parameter symbol min typ max unit microcontroller serial interface timing sclk cycle time tcyc 4t 8t ns sclk high period tsh 2t 4t ns sclk low period tsl 2t 4t ns data setup time tsu 2t 4t ns data hold time thd 2t 4t ns csx rise to sclk wait time twsclk 0t 2t ns sclk to csx rise wait time twcsx 4t 6t ns rise time tsr 50 ns fall time tsf 50 ns audio data timing clock phase (note 2) tph 75 ns clock phase (note 3) tph 1/(128fs) ns data delay time tdd 0 75 ns data setup time tsua 1t ns data hold time thda 1t ns note 1: t = 1/fmclk, fmclk: frequ ency of mclkin pin; example: when fmclk = 10mhz, t = 100ns, 2t = 200ns note 2: lrck and bclk are inputs in slave mode. the mclk timing needs only to be synchronized with lrck and bclk and its phase is irrelevant. note 3: in master mode, lrck and bclk are output in master mode and fs is the sampling frequency. note 4: the load of output pin: 30pf. microcontroller serial interface timing diagram twsclk csb sck a [ 7 ] tsh tsl tcyc tsu thd tsf tsr dn [ 0 ] twcsx sda audio data timing diagram tph lrck bclk a dout tph tdd tsu thd dain LC07410LG no.a1345-11/36 audio data formats ? i 2 s mode lrck bclk a dout 15 14 10 15 14 10 lch data rch data ? left-justified mode lrck bclk a dout 15 14 10 15 14 10 lch data rch data 15 ? right-justified mode lrck bclk a dout 15 14 10 15 14 10 lch data rch data 0 pll/bclk/lrck master/slave pin no. pin name slave mode (pll: off) master mode (pll: on) a7 mclkin input input a6 mclko output (through) output (pll = 256fs) pin no. pin name slave mode (adf_master = 0) master mode (adf_master = 1) b7 lrck input output c6 bclk input output LC07410LG no.a1345-12/36 microcontroller serial interface the internal registers values are written by the serial in terface consisting of the thre e csb, sck, and sda lines. when the csb pin is set low, the lc07410 lg is switched into the mode that enab les operation. the data is received on a byte basis with msb first. continuous access (burst access) is also possible, and th e addresses incremented by 1 are accessed in sequence with each byte following access to the register specified by the address byte. if the size of data exceeding the highest address (39h) is accessed in this process, the data concerned is treat ed as invalid. in other word, the address never wraps around to 00h. transferring data to one address csb sck sda x a [ 7 ] a [ 6 ] a [ 5 ] a [ 4 ] a [ 3 ] a [ 2 ] a [ 1 ] a [ 0 ] d [ 7 ] d [ 6 ] d [ 5 ] d [ 4 ] d [ 3 ] d [ 2 ] d [ 1 ] d [ 0 ] x x x address byte write data (address a) transferring data to contiguous addresses csb sck sda a [ 7 ] a [ 6 ] a [ 5 ] a [ 4 ] a [ 3 ] a [ 2 ] a [ 1 ] a [ 0 ] d0 [ 7 ] d0 [ 6 ] d0 [ 5 ] d0 [ 4 ] d0 [ 3 ] d0 [ 2 ] d0 [ 1 ] d0 [ 0 ] x x address byte write data (address a) x x d1 [ 7 ] d1 [ 6 ] d1 [ 5 ] d1 [ 4 ] d1 [ 3 ] d1 [ 2 ] d1 [ 1 ] d1 [ 0 ] write data (address a+1) dn [ 0 ] a[7:0] : designated address d[7:0] : register data x : invalid LC07410LG no.a1345-13/36 specification details ? power down/system reset when the pdnb pin is set to 0, all the circuits are set to power down mode regardless of the power down settings for each block. a 0 on the pdnb pin also triggers a system reset. after the power is first applied, the system must be reset without fail. [see the section on ?checkpoint_2) resetting?] after resetting, the contents of the serial port register are initialized. the vref buffer is activated by releasing power down mode by setting the pdnb pin from 0 to 1, and then by setting vref_bias[1:0] to 01. when vref_bias [1:0] is set to 10 , vref starts. along with the start of vref, the line output pin is biased to 1/2v dd a. once the vref voltage has stabilized, vref_bias [1:0] must be set to 11 (normal state). reference voltage generator circuit vref _ bias: voltage reference bias * bold letters indicate initial settings. adrs bit name init description 01h [5:4] vref_bias 00b sets the reference voltage circuit (vref pin). 11: normal operation (standard resistor value) 10: quick rise to reference voltage <*1> 01: activates iref bias, vref off 00: power down <*1> the target voltage is reached quickly by connecting a low-resistance element in the ?reference voltage generation circuit.? during normal operation, a standard resistance is recommended in order to save power. power control adrs bit name init description [7] mic_pdx 0b mic amplifier circuit, power control 1: power on 0: power down [6] mic_pwr_pdx 0b mic power circuit (mic_pwr pin), power control 1: power on 0: power down [5] pga_pdx 0b pga circuit, power control 1: power on 0: power down [4] adc_pdx 0b adc circuit, power control 1: power on 0: power down [3] dac_pdx 0b dac circuit, power control 1: power on 0: power down [2] sel_pdx 0b selector (l out 2) circuit, power control 1: power on 0: power down [1] lo_pdx 0b line out circuit (l out 1) circuit, power control 1: power on 0: power down 00h [0] sp_pdx 0b speaker amplifier circuit, power control 1: power on 0: power down [2] pll_pdx 0b pll circuit, power control 1: power on 0: power down (pll-ext mode) [1] reg_pdx 0b regulator circuit, power control 1: power on 0: power down 01h [0] vd_pdx 0b video driver circuit, power control 1: power on 0: power down sampling frequency setting set sampling frequency used by fs [4:0] register. this is necessary to make it for correctly setting digital frequency characteristic and alc damping time constant. the setting is adjusted to a value that is the closest to fs used. adrs bit name init description 15h [3:0] fs 1000b sampling frequency setting 1000: 48khz /0111: 44.1khz/0110: 32khz/0101: 24khz 0100: 22.05khz/0011: 16khz/ 0010: 12khz/0001: 11.025khz 0000: 8khz note: this setting doesn?t synchronize with pll setting. it is necessary to set it individually respectively. refer to the page of pll function explanation for pll setting. LC07410LG no.a1345-14/36 ? 3v regulator built-in 3v regulator for v dd a,v dd p. the regulator starts by setting as reg_pdx = 1. output current is 100ma (typ). it provides with max 200ma (typ) output current limiter for over-current protective function. ? microphone (mic) amplifier the microphone amplifier has a differential input and a gain of +26db (typ). its gain can also be set to +20db or 0db by register mgain [1:0]. its input resistance is 70k (typ). the micpwr is a power output pin for the microphone, and its output voltage is 2.3v (typ 0.767 v dd a). the maximum output current is 20ma. the microphone amplifier is placed in the power down mode by setting mic_pdx to 0. when mic_pwr_pdx is set to 0, the microphone power supply circuit is placed in the power down mode. adrs bit name init description 02h [5:4] mic_gain 01b mic amplifier circuit, gain setting 11: 26db 10: 20db 01: 0db 00: 0db ? recording system automatic level control (alc) the amplifier gain of the pga (programmable gain amplifier) must be automatically adjusted so that the a/d converter output audio level is setup to the predetermined va lue. the gain can be varied within a range (maximum) of -14db to +34db. when using alc in the recording system, set rec_alc to 1 and pb_alc to 0 (recording system alc mode). when rec_alc is set to 0 and pb_alc is set to 0 (alc off mode), the pga is placed in the manual mode, and the amplifier gain is fixed to the valu e of the alc_gain register setting. when pga_pdx is set to 0, the pga is placed in the powe r down mode. during normal use, the state of pga_pdx must be switched at the same time as adc_pdx. for further details on operation, refer to ?description of alc/limiter (automatic level control) operation.? any of eight recording alc levels (in 1db steps from -3dbfs to -10dbfs) can be set using the alc_val register. adrs bit name init description [6:4] alc_val 001b set the alc limiter level 000: -3dbfs 001: -4dbfs 010: -5dbfs 011: -6dbfs 100: -7dbfs 101: -8dbfs 110: -9dbfs 111: -10dbfs 03h [2:0] alc_fa1 010b attack coefficient 1 setting [6:4] alc_tha 010b set the attack speed switch over thresh 04h [2:0] alc_fa2 100b attack coefficient 2 setting [6:4] alc_thr1 011b set the recovery speed switch over thresh1 05h [2:0] alc_fr1 100b recovery coefficient 1 setting [6:4] alc_thr2 011b set the recovery speed switch over thresh2 06h [2:0] alc_fr2 100b recovery coefficient 2 setting 07h [2:0] alc_fr3 100b recovery coefficient 3 setting [7] alc_fullen 0b sets the full scale detection mode 1: performs attack operation regardless of th e alczcd setting when a full scale is detected. 0: normal operation [6] alc_zcd 1b controls the gain change operation at zerocross timing. 1: changes the gain at zerocross timing. 0: changes the gain without waiting for a zerocross timing. [5:4] alc_zcdtm 01b set the zerocross detectio n timeout time. valid when [alc_zcd] = 1. 11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs * it becomes the above-mentioned 1/4 times at fs 8k to12khz, it becomes the above-mentioned 1/2 times at fs 16k to 24khz. [3:2] alc_tlim 01b set the inter-zerocross attack limit. 11: 4db 10: 2db 01: 1db 00: 0.5db valid when [alc_zcd] = 1 08h [1:0] alc_rwt 10b set the recovery alert time 11: 1024/fs 10: 512/fs 01: 256/fs 00: 128/fs * it becomes the above-mentioned 1/ 4 times at fs 8k to 12khz, it becomes the above-mentioned 1/2 times at fs 16k to 24khz. continued on next page. LC07410LG no.a1345-15/36 continued from preceding page. adrs bit name init description [7] alc_ngen 0b set th e noise gate function 1: valid 0: invalid [6:4] alc_ngth 100b set the noise gat e silent detection thresh level [3:2] alc_ngdt 10b set the noise gate silent detection time/see the gain attenuation time 09h [1:0] alc_ngrt 01b set the noise gate reset time 0bh [5:0] alc_vmax 0eh set the maximum pga gain value (init value = 0eh: 0db) refer to ?alc circuit gain setting table.? 0ch [5:0] alc_gain 0eh set the manual mode pga gain value (init value = 0eh: 0db) refer to ?alc circuit gain setting table.? 0dh [1:0] rec_alc pb_alc 10b alc mode setting 10: rec alc, pb manual gain setting 01: pb alc, rec manual gain setting 00/11: alc off, rec/pb manual gain setting see the section on "description of alc operation." ? attack coefficient 1 ? attack coefficient 2 fa1[2:0] 1db attenuation time* fs = 48khz 24khz 12khz fa2[2:0] 1db attenuation time* fs = 48khz 24khz 12khz 000 1/fs 20.83 s 000 1/fs 20.83 s 001 2/fs 41.67 s 001 2/fs 41.67 s 010 4/fs 83.33 s 010 4/fs 83.33 s 011 8/fs 166.7 s 011 8/fs 166.7 s 100 16/fs 333.3 s 100 2 9 /fs 10.66ms 101 32/fs 666.6 s 101 2 10 /fs 21.33ms 110 64/fs 1.333ms 110 2 11 /fs 42.67ms 111 128/fs 2.666ms 111 2 12 /fs 85.33ms * at fs = 32k to 48khz setting. 1/4 times at 8k to 12khz, 1/2 times at 16k to 24khz (48khz, 24khz, 12khz become the same speed) . ? attack speed switch over thresh level tha[2:0] level to alc_val 000 +1db 001 +2db 010 +3db 011 +4db 100 +5db 101 +6db 110 +7db 111 +8db ? recovery coefficient 1 ? recovery coefficient 2 ? recovery coefficient 3 fr1[2:0] fs/s* fr2[2:0] fs/s* fr3[2:0] fs/s* 000 13.2 000 3.3 000 0.828 001 6.6 001 1.65 001 0.424 010 3.3 010 0.828 010 0.212 011 1.65 011 0.424 011 0.106 100 0.828 100 0.212 100 0.053 101 0.424 101 0.106 101 0.026 110 0.212 110 0.053 110 0.013 111 0.106 111 0.026 111 0.006 * value at fs = 48khz, 24khz, 12khz LC07410LG no.a1345-16/36 ? recovery speed switch over thresh level 1 ? recovery speed switch over thresh level 2 thr1[2:0] level to alc_val thr2[2:0] level to alc_val 000 -26db 000 -20db 001 -24db 001 -18db 010 -22db 010 -16db 011 -20db 011 -14db 100 -18db 100 -12db 101 -16db 101 -10db 110 -14db 110 -8db 111 prohibition 111 prohibition ? zerocross timeout period ? recovery alert time zcdtm[1:0] timeout period* fs = 48k/24k/12khz rwt[1:0] standby time fs = 48k/24k/12khz 00 1024/fs 21.33ms 00 128/fs 2.67ms 01 2048/fs 42.67ms 01 256/fs 5.33ms 10 4096/fs 85.33ms 10 512/fs 10.67ms 11 8192/fs 170.7ms 11 1024/fs 21.33ms * at fs = 32k to 48khz setting. 1/4 times at 8k to 12khz, 1/2 times at 16k to 24khz (48khz, 24khz, 12khz become the same speed) . alc circuit gain setting table alc_vmax[5:0]/alc_gain[5:0] [5:0] gain [5:0] gain [5:0] gain [5:0] gain [5:0] gain 00h -14db 0ah -4db 14h 6db 1eh 16db 28h 26db 01h -13db 0bh -3db 15h 7db 1fh 17db 29h 27db 02h -12db 0ch -2db 16h 8db 20h 18db 2ah 28db 03h -11db 0dh -1db 17h 9db 21h 19db 2bh 29db 04h -10db 0eh 0db 18h 10db 22h 20db 2ch 30db 05h -9db 0fh 1db 19h 11db 23h 21db 2dh 31db 06h -8db 10h 2db 1ah 12db 24h 22db 2eh 32db 07h -7db 11h 3db 1bh 13db 25h 23db 2fh 33db 08h -6db 12h 4db 1ch 14db 26h 24db 30h 34db 09h -5db 13h 5db 1dh 15db 27h 25db ? noise gate silent detection thresh ? noise gate silent detection time/gain attenuation speed (0db -35db) ngth[2:0] thresh ngdt[1:0] detection time* fs = 48khz 24khz 12khz gain attenuation time* fs = 48khz 24khz 12khz 000 -35dbfs 00 2 13 /fs 0.17s 30 2 10 /fs 0.64s 001 -41dbfs 01 2 14 /fs 0.34s 30 2 11 /fs 1.28s 010 -47dbfs 10 2 15 /fs 0.68s 30 2 12 /fs 2.56s 011 -53dbfs 11 2 16 /fs 1.36s 30 2 13 /fs 5.12s 100 -59dbfs 101 -65dbfs 110 -71dbfs 111 -77dbfs * at fs = 32k to 48khz setting. 1/4 times at 8k to 12khz, 1/2 ti mes at 16k to 24khz ? noise gate reset time (-35db 0db) ngrt[1:0] gain reset time* fs = 48khz 24khz 12khz 00 30 2 8 /fs 0.16s 01 30 2 9 /fs 0.32s 10 30 2 10 /fs 0.64s 11 30 2 11 /fs 1.28s * at fs = 32k to 48khz setting. 1/4 times at 8k to 12khz, 1/2 times at 16k to 24khz (48khz, 24khz, 12khz become the same speed) . LC07410LG no.a1345-17/36 relation between output level and recovery speed (fr,thr) fr2 fr1 fr3 alc val thr2 thr1 signal after a dc fr value is shown by inclination (fs/s) of the shape of recovery waves. (fs = full scale = 0dbfs) description of alc/limiter (automatic level control) operation note: whatever is contained inside the parentheses ? ? is applicable in the pb-alc mode. the amplifier gain ?digital volume value? of the pga (program mable gain amplifier) is automatically adjusted so that the a/d converter output audio level ?digital volume output? is set to the alc value ?alc_val [2:0]?. the pga ?digital volume? gain can be varied in the -14db to +34db range. the maximum value ?alc_vmax [5:0]? can be set in this variable range. ? alc settings power-saving function when [pga_pdx] is 0, the alc circuit and pga circuit are set to power down mode. manual function (alc off) at rec_alc = pb_alc = 0, it become manual mode. pga gain is fixed by value of alc_gain [5:0] digital volume value is fixed by evr_gain [6:0] system operation alc is performed by feeding back the a/d converter ?digital volume? data. accordingly, configure the settings as shown in the table below in order for the alc functions to be activated. (1) attack operations when the adc ?digital volume? output exceeds the alc limiter level, alc_val[2:0], the pga gain ?digital volume value? is lowered. when the rate of gain attenu ation is alc_tha[2:0] or more, alc_fa1[1:0] results, but when the value is less than alc_ tha[2:0], alc_fa2[1:0] results. when zero-cross detection alc_zcd is set to 1, the gain attenuation from zero-cross to zero-cross is limited by the limit value alc_tlim[1:0]. mode resister rec-alc pb-alc pga_pdx 1 0 adc_pdx 1 x dac_pdx x 1 rec_alc 1 0 pb_alc 0 1 LC07410LG no.a1345-18/36 (2) recovery operations when the adc ?digital volume? output is less than 2db of the alc limiter level, alc_val[1:0], and this status continues for the recovery wait time, alc_rwt[1:0], the pga gain ?digital volume value? is increased. the rate of gain increase is performed using the recovery coefficients given below according to the amplitude. recovery coefficients by level output level LC07410LG no.a1345-20/36 audio data formats adrs bit name init description [3] ad_mute 0b sets the adc output mute 1: enables mute function 0: disables mute function 0dh [2] fbclk 0b sets the bclk frequency 1: 32fs 0: 64fs [4] adf_master 0b adf circuit 1: master mode, bclk and lrclk pins are set for output. 0: slave mode, bclk and lrclk pins are set for input. [3] adf_dac_inv 0b sets the dac input data of the adf circuit. 1: inverted 0: non-inverted [2] adf_adc_inv 0b sets the adc input data of the adf circuit. 1: inverted 0: non-inverted 0eh [1:0] adf_mode 00b define the data format of the adf circuit. 11, 10: right justificat ion (right-justified) 01: left justification (left-justified) 00: i 2 s see the section on "audio data formats." ? loopback (a) loopback mode (adf_lb = 1) internal connect between adout and dain, this enables the mic input to be output to the line or speaker without recording or playback op eration. in this case, external output through adout is enabled but external input through dain is disabled. (b) standard mode (adf_lb = 0) the dain external input is enabled and the in ternal switch for adout and dain is released. adout dain i/f adrs bit name init description 0fh [5] adf_lb 0b loopback setting 1: adc internal loopback in dac is done 0: adc internal loopback in dac is not done programmable digital filter adc dain programmable filter 1 windcut hpf programmable filter 2 adout dac ? windcut hpf (1st order) wind_cut [5:4] turns off the high-pass filter (through) when initialized to (00). regardless of the sampling frequency (fs), the cutoff frequenc y (fc) is 400hz when wind_cut [5:4] is set at 11, 300hz at 10, 200hz at 01 and off at 00. adrs bit name init description 0dh [5:4] wind_cut 00b wind_cut function (hpf fc setting) 11: 400hz 10: 300hz 01: 200hz 00: off LC07410LG no.a1345-21/36 ? programmable filter a second order biquad filter that allows coefficients to be freely set is used for the programmable filter. a notch filter, lpf, or other filter can be configured by setting the coefficients, a1, a2, b0, b1, and b2, in 16-bit 2?s complement notation in a register. make sure that th e corresponding filter is off when setting or modifying coefficients. adrs bit name init description [7] filter2 0b set the programmable filter2 1: on 0: off 0dh [6] filter1 0b set the programmable filter1 1: on 0: off 1bh [7:0] a1[15:8] 00h 1ch [7:0] a1[7:0] 00h set the programmable filter1 coefficient a1 1dh [7:0] a2[15:8] 00h 1eh [7:0] a2[7:0] 00h set the programmable filter1 coefficient a2 1fh [7:0] b0[15:8] 40h 20h [7:0] b0[7:0] 00h set the programmable filter1 coefficient b0 21h [7:0] b1[15:8] 00h 22h [7:0] b1[7:0] 00h set the programmable filter1 coefficient b1 23h [7:0] b2[15:8] 00h 24h [7:0] b2[7:0] 00h set the programmable filter1 coefficient b2 25h [7:0] a1[15:8] 00h 26h [7:0] a1[7:0] 00h set the programmable filter2 coefficient a1 27h [7:0] a2[15:8] 00h 28h [7:0] a2[7:0] 00h set the programmable filter2 coefficient a2 29h [7:0] b0[15:8] 40h 2ah [7:0] b0[7:0] 00h set the programmable filter2 coefficient b0 2bh [7:0] b1[15:8] 00h 2ch [7:0] b1[7:0] 00h set the programmable filter2 coefficient b1 2dh [7:0] b2[15:8] 00h 2eh [7:0] b2[7:0] 00h set the programmable filter2 coefficient b2 ? dsp route setting the route of digital filter is select ed by the sel_use_dsp register. adrs bit name init description 0fh [1] sel_use_dsp 0b dsp route setting 1: dsp inserted in pb (dac) side 0: dsp inserted in rec (adc) side note: programmable filter and wind cut hpf functions serve as the dsp functions. LC07410LG no.a1345-22/36 ? digital volume contained inside the d/a converter is a digital volume control, and by setting evr_gain [6:0], the gain level can be attenuated from +12db (max) to -64db or muted. when evr_zcd is 0, the gain is change d immediately after setting evr_gain [6:0]. when evr_zcd is 1, after setting evr_gain [6:0] the gain is changed at the zero cross timing of the audio signals. the timeout time for zero cross detection can be set using evr_zcdtm [1:0]. when evr_softsw is 1, the soft switc hing operation is performed, and after the evr_gain [6:0] setting has been changed, the gain automatically changes in 1-step increments until it arrives at the predetermined value. the period of gain change can be set using evr_ssc [1:0]. if evr-softsw is set to 1 and evr_zcd is set to 1, the d/a converter, after the lapse of the time defined by evr_ssc[1:0], repeats the cycle of waiting for the next zero cr oss point and changing the gain by 1 increment, until the predetermined volume value is reached. adrs bit name init description [7] evr_mute 1b controls the mute f unction of the evr (digital) circuit. 1: enables mute function. 0: disables mute function. 10h [6:0] evr_gain 00h controls the gain function of the evr (digital) circuit. 00h: -64db 57h: +12db to 2ch: -9.5db/0.5db step 2bh: -10db to 0ch: -41db/1.0db step 0bh: -42db to 00h: -64db/2.0db step [6] evr_volzcd 1b controls the gain change operation of the evr (digital) circuit at zerocross timing. 1: changes the gain at the zerocross timing. 0: changes the gain without waiting for a zerocross timing. [5:4] evr_zcdtm 01b set the zerocr oss detection timeout time of the evr (digital) circuit. 11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs valid when [evr_zcd] = 1 [2] evr_softsw 1b controls the soft switch function of the evr (digital) circuit. 1: on 0: off 11h [1:0] evr_voltm 00b set the time of the soft switch function of the evr (digital) circuit (dos not depend on fs). 11, 10: inhibited 01: 2.278ms/step, (200ms: when +12db ? mute) 00: 1.142ms/step , (100ms: when +12db ? mute) digital evr circuit gain setting table evr_gain [6:0] [6:0] gain [6:0] gain [6:0] gain [6:0] gain [6:0] gain 00h -64db 12h -35db 24h -17db 36h -4.5db 48h +4.5db 01h -62db 13h -34db 25h -16db 37h -4db 49h +5db 02h -60db 14h -33db 26h -15db 38h -3.5db 4ah +5.5db 03h -58db 15h -32db 27h -14db 39h -3db 4bh +6db 04h -56db 16h -31db 28h -13db 3ah -2.5db 4ch +6.5db 05h -54db 17h -30db 29h -12db 3bh -2db 4dh +7db 06h -52db 18h -29db 2ah -11db 3ch -1.5db 4eh +7.5db 07h -50db 19h -28db 2bh -10db 3dh -1db 4fh +8db 08h -48db 1ah -27db 2ch -9.5db 3eh -0.5db 50h +8.5db 09h -46db 1bh -26db 2dh -9db 3fh +0db 51h +9db 0ah -44db 1ch -25db 2eh -8.5db 40h +0.5db 52h +9.5db 0bh -42db 1dh -24db 2fh -8db 41h +1db 53h +10db 0ch -41db 1eh -23db 30h -7.5db 42h +1.5db 54h +10.5db 0dh -40db 1fh -22db 31h -7db 43h +2db 55h +11db 0eh -39db 20h -21db 32h -6.5db 44h +2.5db 56h +11.5db 0fh -38db 21h -20db 33h -6db 45h +3db 57h +12db 10h -37db 22h -19db 34h -5.5db 46h +3.5db 11h -36db 23h -18db 35h -5db 47h +4db LC07410LG no.a1345-23/36 ? playback system automatic level control (alc) when rec_alc is set to 0 and pb_alc is set to 1 (playback system alc mode), the digital volume control functions as the playback system alc. subject the volume value to automatic adjustment so that the digital volume output level is set to the predetermined value. for further details on operation, refer to ?descriptio n of alc/limiter (automatic level control) operation.? noise gate function (ngen) setting is disabled if playback system alc mode. when rec_alc is set to 0 and pb_alc is set to 0 (alc off mode), the digital volume control is set to manual mode, and the gain is fixed to the evr_gain [6:0] register setting. ? line amplifier the line amplifier provides a gain of 0db, +4db, +6db or +8db. when lo_mute is set to 1, the line output is muted. when lo_pdx is set to 0, the line amplifier is placed in the power down mode. if the line output is set to the high-i mpedance state when the line amplifier is placed in the power down mode, lo _ vrefsw must be set to 0. adrs bit name init description [7] lo_mute 1b controls the mute functi on of the line out circuit. 1: enables mute function. 0: disables mute function. [6] lo_vrefsw 1b state setting when power of line output id downed* 1: connects to the reference power source (vref). 0: does not connect to the reference power source (vref). 12h [5:4] lo_gain 10b select the gain of the line out circuit. 11: +8db 10: +6db 01: +4db 00: 0db * it is not possible to connect between line out and vref by setting lo_vrefsw to 1 even if lo_pdx is set to 1. ? speaker amplifier the speaker amplifier must be started after the selector am plifier output (lout2) has been activated and the voltage has stabilized. either 0db or +6db can be selected as th e selector amplifier gain using the sel_gain setting. v dd s in the range of 2.7v to 5.5v is supported. (piezoelectric speaker supported) the amplifier gain is 6db (+12db with the btl output). (with an 8 load) the spkin input resistance is 10k (type). when sp_pdx is set to 0, the speaker am plifier is placed in the power down mode. depending on v dd s, one of the four speaker terminal voltages can be selected using sp_bais [1:0] to achieve an optimal dynamic range. ? thermal shutdown if a chip temperature of 140 c or higher is detected while sp_tsd_en is se t 1, the speaker amplifier is placed in the power down mode for protection. the thermal shutdown function is disabled if sp _ tsd _ en is set to 0. adrs bit name init description [2] sel_gain 0b selector circuit, gain selection 1: +6db 0: 0db 12h [1:0] sel_in 01b selector input selection setting 00: prohibition 01: dac 10: alc 11: prohibition [3:2] sp_idl 10b set the idling current of the speaker amplifier circuit 11: 2.0ma 10: 1.0ma 01: 0.67ma 00: 0.5ma 13h [1:0] sp_bias 00b set the bias control of the speaker amplifier circuit 11: 0.833 v dd a 10: 0.766 v dd a 01: 0.666 v dd a 00: 0.5 v dd a [7] sp_out_en 0b enables or disables the speaker amplifier circuit 1: on 0: off 14h [6] sp_tsd_en 1b enables or disables the thermal shut down function of the speaker amplifier circuit 1: on 0: off see the section on "speaker amplifier start/stop sequence" LC07410LG no.a1345-24/36 ? beep output a signal input from the beep pin or a beep sound (pulse wave) generated within the ic can be output from the speaker. (a) ext-beep operation when bpmode is 01, the signal input to the beep pin is output from the speaker. (b) int-beep operation when bpmode is 10/11, a beep signal generate d within the ic is output from the speaker. intbpst beep output nrep fsig to n to ff use the bphz register to set the pulse frequency, fsig ,the bpton and bptoff registers to set the on/off duty, and the bpcnt register to set the repeat count, nrep. then set intbpst = 0 1 to output the beep sound. output stops automatically when the specifi ed number of beeps output. when bpmode is 10 (serial control mode), intbpst control is carried out according to registers. when bpmode is 11 (parallel control mode), in tbpst control is carried out using the beep pin. note: when the transition intbpst = 0 1 is detected, the beep sound starts. when bpmode is 10 (serial control mode), the beep sound is not output even if intbpst = 1 is sent when intbpst is set to 1. if toff is 0, the continuous beep sound is output during the period given by ton*nrep. if nrep is set to infinite, the ton/toff cycle repeats infinitely and stops when intbpst is set to 0. output stops when intbpst is set to 0, even in the middle of beep output. the gain from the start of beep input until btl output can be varied within the range -15db to -21db, based on the sp_bpvol[1:0] setting. it is also possible to adjust the sound volume us ing an external resistor and by setting of 0db. [againof approximately -21db (typ) results with an external 100k connection.] adrs bit name init description [7:6] bpmode 00b beep output mode setting 11: int-beep operation/parallel control mode 10: int-beep operation/serial control mode 01: ext-beep operation 00: off 13h [5:4] bpvol 11b beep gain selection 11: -21db 10: -18db 01: -15db 00: 0db [7:5] bpton 010b int-beep on duty (ton) setting 2fh [4:0] bptoff 00110b int-beep off duty (toff) setting [7] intbpst 0b int-beep starting control (at bpmode = 10, valid) [6:4] bphz 011b int-beep frequency (fsig) setting 30h [3:0] bpcnt 0110b int-beep number of cycles (nrep) setting LC07410LG no.a1345-25/36 bphz[2:0] fsig bpton[2:0] ton bptoff[4:0] toff bptoff[4:0] toff 000 1khz 000 20ms 00000 0ms 01011 210ms 001 2khz 001 40ms 00001 10ms 01100 230ms 010 3khz 010 60ms 00010 30ms 01101 250ms 011 4khz 011 80ms 00011 50ms 01110 270ms 100 5khz 100 100ms 00100 70ms 01111 290ms 101 6khz 101 120ms 00101 90ms 10000 310ms 110 7khz 110 140ms 00110 110ms 10001 330ms 111 8khz 111 160ms 00111 130ms 10010 350ms 01000 150ms 10011 370ms 01001 170ms 10100 390ms 01010 190ms bpcnt[3:0] nrep bpcnt[3:0] nrep 0000 infinite 1000 8 0001 1 1001 9 0010 2 1010 10 0011 3 1011 11 0100 4 1100 12 0101 5 1101 13 0110 6 1110 14 0111 7 1111 15 ? pll (a) pll mode (pll_pdx = 1) in this mode, the 256fs clock (mclk) used by the codec block is generated from the clock (12, 13.5, 24 and 27mhz frequencies supported) which is input from mclkin, and bclk and lrck are output. sampling frequencies (fs) of 7.86khz to 48khz are supported. fs setting fs is set by setting the division ratio for each of the thr ee frequency dividers (div1, div2, and div3) in respective registers. 1. set fcki[2:0] for the mclkin frequency, results in 12mhz or 13.5mhz as the frequency input to div1. 2. set div1, div2, and div3, while referring to the division ratio setting example table. ex. "fcki = 2, div1 = 125, div2 = 128, div3 = 2" in case of "mclkin = 24mhz, fs = 24khz" (b) ext mode (pll_pdx = 0) in this mode, the 256fs clock (mclk) from mclkin is input and used. when adf_master is 1, bclk and lrck whose frequency is obtained by dividing the frequency of mclkin are output. when adf_master is 0, blck and lrck are external inputs. * in the codec block, bclk and lrck must be synchronized with mclk. in pll mode (pll_pdx = 1), operation must be performed in bclk output mode (adf_master = 1). in ext mode (pll_pdx = 0) and when adf_master is 0, bclk and lrck synchronized with mclk must be input. 256fs div3 div1 fcki div2 mclkin f mckout f = = LC07410LG no.a1345-26/36 pll block diagram 1/4 1/2 1/2 mclkin div1 24mhz 12mhz or 13.5mhz 27mhz div2 pll pll_div2 pll_div1 div3 ext pll 1/8 (32fs) 1/4 (64fs) fbclk pll_pdx 1/256 adf_master codec sel_mclko mckout lrck bclk pll_fck1[2:0] h l adrs bit name init description 0dh [2] fbclk 0b sets the bclk frequency 0: 64fs 1: 32fs 0eh [4] adf_master 0b sets the bclk, lrck master/slave 0: slave 1: master 16h [5:4] sel_mclko 00b mclko output selection 00: ?l? 10: ?h? 01/11: mclkin[pll_pdx = 0] or pll output [pll_pdx = 1] 16h 17h [0] [7:0] pll_div1 07dh sets the basis clock frequency ratio (div1) 000h: prohibition 001h: 1/1 to 1ffh: 1/511 default: 07dh(125) 18h 19h [0] [7:0] pll_div2 080h sets the vco output frequency ratio (div2) 000h: prohibition 001h: 1/1 to 1ffh: 1/511 default: 080h(128) [1:0] pll_div3 00b sets the mclk output frequency ratio (div3) 00: 1/1 01: 1/2 10: 1/4 11: 1/4 1ah [5:4] pll_fcki 00b sets the mc lkin input frequency ratio 00: 1/1 01: 1/2 10: 1/4 11: 1/4 frequency ratio setting example div1 input = 12mhz div1 input = 13.5mhz target frequency frequency ratio value frequency ratio value fs(khz) 256fs(mhz) div1 div2 div3 div1 div2 div3 48 12.288 125 128 1 245 223 1 44.1 11.29 304 286 1 171 143 1 32 8.192 271 185 1 206 125 1 24 6.144 125 128 2 245 223 2 22.05 5.6448 304 286 2 171 143 2 16 4.096 271 185 2 206 125 2 12 3.072 125 128 4 245 223 4 11.025 2.8224 304 286 4 171 143 4 8 2.048 271 185 4 206 125 4 LC07410LG no.a1345-27/36 ? video driver vdref reg vref2 vref1 att 0db vdin -6/0db lpf 12db vd_dctl vd_gain vdout 75 0.1v vdin sync dc: state of -12.5mv to 162.5mv (at 12.5mv/step, +12db), -25mv to 325mv (25mv/step, at +6db) is adjustable to vdout sync dc (100mv). either 6db or 12db can be selected as the total gain of th e video amplifier using the intern al register setting (vd_gain). when the input sync level is within the -12.5mv to 162.5mv (at +12db)/-25mv to 325mv (at 6db) range, the output sync level can be adjusted to 100mv using the internal register settings (vd_dctl [3 : 0]). adrs bit name init description [4] vd_gain 0b selects the driver gain of the video circuit 0: +6db 1: +12db 14h [3:0] vd_dctl 0001b selects the input sync level dc offset of the video circuit 0000: -25mv to 1110: 325mv (+6db) 0000: -12.5mv to 1110: 162.5mv (+12db) video driver sync dc level adjustment table vd_dctl[3:0] input_sync_dc at +6db input_sync_dc at +12db output_sync_dc 0000 -25mv -12.5mv 100mv 0001 0mv 0mv 100mv 0010 25mv 12.5mv 100mv 0011 50mv 25mv 100mv 0100 75mv 37.5mv 100mv 0101 100mv 50mv 100mv 0110 125mv 62.5mv 100mv 0111 150mv 75mv 100mv 1000 175mv 87.5mv 100mv 1001 200mv 100mv 100mv 1010 225mv 112.5mv 100mv 1011 250mv 125mv 100mv 1100 275mv 137.5mv 100mv 1101 300mv 150mv 100mv 1110 325mv 162.5mv 100mv 1111 0mv 0mv 100mv LC07410LG no.a1345-28/36 register table adrs (address): displayed in hexadecimal notation, init (initial value): displayed in hexadecimal notation register bits indicated by "0" must be set to 0. registers indicated with a gray background are fo r ic testing and their initial values are fixed. all registers (addresses: 00 to 25h) must be load ed with write data (including test registers). register data d[7:0] functions adrs [7:0] init 7 6 5 4 3 2 1 0 pm1 00h 00h mic_pdx mic_pwr_pdx pga_pdx adc_pdx dac_pdx sel_pdx lo_pdx sp_pdx pm2 01h 00h sync_clr 0 vref_bias[1] vref_bias[0] 0 pll_pdx reg_pdx vd_pdx mic 02h 10h 0 0 mic_gain[1] mic_gain[0] 0 0 0 0 alc1 03h 12h 0 alc_val[2] alc_val[1] alc_val[0] 0 alc_fa1[2] alc_fa1[1] alc_fa1[0] alc2 04h 24h 0 alc_tha[2] alc_tha[1] alc_tha[0] 0 alc_fa2[2] alc_fa2[1] alc_fa2[0] alc3 05h 34h 0 alc_thr1[2] alc_thr1[1] alc_thr1[0] 0 alc_fr1[2] alc_fr1[1] alc_fr1[0] alc4 06h 34h 0 alc_thr2[2] alc_thr2[1] alc_thr2[0] 0 alc_fr2[2] alc_fr2[1] alc_fr2[0] alc5 07h 04h 0 0 0 0 0 alc_fr3[2] alc_fr3[1] alc_fr3[0] alc6 08h 56h alc_fullen alc_zcd alc_zcdtm[1] alc_zcdtm[0] alc_tlim[1] alc_tlim[0] alc_rwt[1] alc_rwt[0] alc7 09h 49h alc_ngen alc_ngth[2] alc_ngth[1] alc_ngth[0] alc_ngdt[1] alc_ngdt[0] alc_ngrt[1] alc_ngrt[0] alc8 0ah 0ah 0 0 0 0 1 0 1 0 alc9 0bh 0eh 0 0 alc_vmax[5] alc_vmax[4] alc_vmax[3] alc_vmax[2] alc_vmax[1] alc_vmax[0] alc10 0ch 0eh 0 0 alc_gain[5] alc_gain[4] alc_ gain[3] alc_gain[2] alc_gain[1] alc_gain[0] codec1 0dh 02h filter2 filter1 wind_cut[1] wind_cut[0] ad_mute fbclk rec_alc pb_alc codec2 0eh 00h 0 0 0 adf_master adf_dac_inv adf_adc_inv adf_mode[1] adf_mode[0] codec3 0fh 00h 0 0 adf_lb 0 0 0 sel_use_dsp 0 evr1 10h 80h evr_mute evr_gain[6] evr_gain[5] evr_gain[4] evr_gain[3] evr_gain[2] evr_gain[1] evr_gain[0] evr2 11h 54h 0 evr_volzcd evr_zcdtm[1] evr_zcdtm[0] 0 evr_softsw evr_voltm[1] evr_voltm[0] line/sel 12h e1h lo_mute lo_vrefsw lo_gain[1] lo_gain[0] 0 sel_gain sel_in[1] sel_in[0] spk1 13h 38h bpmode[1] bpmode[0] bpvol[1] bpvol[0] sp_idl[1] sp_idl[0] sp_bias[1] sp_bias[0] spk2/video 14h 41h sp_out_en sp_tsd_en 0 vd_gain vd_dctl[3] vd_dctl[2] vd_dctl[1] vd_dctl[0] fs 15h 08h 0 0 0 0 fs[3] fs[2] fs[1] fs[0] pll1_1 16h 00h 0 0 sel_mclko[1] sel_mclko[0] 0 0 0 pll_div1[8] pll1_2 17h 7dh pll_div1[7] pll_div1[6] pll_div1[5] pll_div1[4] pll_div1[3] pll_div1[2] pll_div1[1] pll_div1[0] pll2_1 18h 00h 0 0 0 0 0 0 0 pll_div2[8] pll2_2 19h 80h pll_div2[7] pll_div2[6] pll_div2[5] pll_div2[4] pll_div2[3] pll_div2[2] pll_div2[1] pll_div2[0] pll3 1ah 00h 0 0 pll_fcki[1] pll_fcki[0] 0 0 pll_div3[1] pll_div3[0] filter1_a1 1bh 00h a1[15] a1[14] a1[13] a1[12] a1[11] a1[10] a1[9] a1[8] filter1_a1 1ch 00h a1[7] a1[6] a1[5] a1[4] a1[3] a1[2] a1[1] a1[0] filter1_a2 1dh 00h a2[15] a2[14] a2[13] a2[12] a2[11] a2[10] a2[9] a2[8] filter1_a2 1eh 00h a2[7] a2[6] a2[5] a2[4] a2[3] a2[2] a2[1] a2[0] filter1_b0 1fh 40h b0[15] b0[14] b0[13] b0[12] b0[11] b0[10] b0[9] b0[8] filter1_b0 20h 00h b0[7] b0[6] b0[5] b0[4] b0[3] b0[2] b0[1] b0[0] filter1_b1 21h 00h b1[15] b1[14] b1[13] b1[12] b1[11] b1[10] b1[9] b1[8] filter1_b1 22h 00h b1[7] b1[6] b1[5] b1[4] b1[3] b1[2] b1[1] b1[0] filter1_b2 23h 00h b2[15] b2[14] b2[13] b2[12] b2[11] b2[10] b2[9] b2[8] filter1_b2 24h 00h b2[7] b2[6] b2[5] b2[4] b2[3] b2[2] b2[1] b2[0] filter2_a1 25h 00h a1[15] a1[14] a1[13] a1[12] a1[11] a1[10] a1[9] a1[8] filter2_a1 26h 00h a1[7] a1[6] a1[5] a1[4] a1[3] a1[2] a1[1] a1[0] filter1_a2 27h 00h a2[15] a2[14] a2[13] a2[12] a2[11] a2[10] a2[9] a2[8] filter1_a2 28h 00h a2[7] a2[6] a2[5] a2[4] a2[3] a2[2] a2[1] a2[0] continued on next page LC07410LG no.a1345-29/36 continued from precceding page. register data d[7:0] functions adrs [7:0] init 7 6 5 4 3 2 1 0 filter1_b0 29h 40h b0[15] b0[14] b0[13] b0[12] b0[11] b0[10] b0[9] b0[8] filter1_b0 2ah 00h b0[7] b0[6] b0[5] b0[4] b0[3] b0[2] b0[1] b0[0] filter1_b1 2bh 00h b1[15] b1[14] b1[13] b1[12] b1[11] b1[10] b1[9] b1[8] filter1_b1 2ch 00h b1[7] b1[6] b1[5] b1[4] b1[3] b1[2] b1[1] b1[0] filter1_b2 2dh 00h b2[15] b2[14] b2[13] b2[12] b2[11] b2[10] b2[9] b2[8] filter1_b2 2eh 00h b2[7] b2[6] b2[5] b2[4] b2[3] b2[2] b2[1] b2[0] spk_beep1 2fh 46h bpton[2] bpton[1] bpton[0] bptoff[4] bptoff[3] bptoff[2] bptoff[1] bptoff[0] spk_beep2 30h 36h intbpst bphz[2] bphz[1] bphz[0] bpcnt[3] bpcnt[2] bpcnt[1] bpcnt[0] test1 31h 00h 0 0 0 0 0 0 0 0 test2 32h 00h 0 0 0 0 0 0 0 0 test3 33h 00h 0 0 0 0 0 0 0 0 test4 34h 9dh 1 0 0 1 1 1 0 1 test5 35h 10h 0 0 0 1 0 0 0 0 test6 36h a3h 1 0 1 0 0 0 1 1 test7 37h 01h 0 0 0 0 0 0 0 1 test8 38h 21h 0 0 1 0 0 0 0 1 test9 39h 00h 0 0 0 0 0 0 0 0 register description adrs bit name init description [7] mic_pdx 0b mic amplifier circuit, power control 1: power on 0: power down [6] mic_pwr_pdx 0b mic power circuit, power control 1: power on 0: power down [5] pga_pdx 0b pga circuit, power control 1: power on 0: power down [4] adc_pdx 0b adc circuit, power control 1: power on 0: power down [3] dac_pdx 0b dac circuit, power control 1: power on 0: power down [2] sel_pdx 0b selector circuit, power control 1: power on 0: power down [1] lo_pdx 0b line out circuit circuit, power control 1: power on 0: power down 00h [0] sp_pdx 0b speaker amplifier circuit, power control 1: power on 0: power down [7] sync_clr 0b internal logic clear 1: on 0: off(normal operation) [5] [4] vref_bias 00b reference voltage circuit (vref pin) setting 00: power down 11: normal operation 10: quick rise to reference voltage 01: iref on/vref off [2] pll_pdx 0b pll circuit, power control 1: power on 0: power down [1] reg_pdx 0b reg circuit, power control 1: power on 0: power down 01h [0] vd_pdx 0b video driver circuit, power control 1: power on 0: power down 02h [5:4] mic_gain 01b mic amplifier circuit, gain setting 11: +26db 10: +20db 01: 0db 00: 0db [6:4] alc_val 001b set the alc limiter level 000: -3dbfs 001: -4dbfs 010: -5dbfs 011: -6dbfs 100: -7dbfs 101: -8dbfs 110: -9dbfs 111: -10dbfs 03h [2:0] alc_fa1 010b attack coefficient 1 setting [6:4] alc_tha 010b set the attack speed switch over thresh 04h [2:0] alc_fa2 100b attack coefficient 2 setting [6:4] alc_thr1 011b set the recovery speed switch over thresh 1 05h [2:0] alc_fr1 100b recovery coefficient 1 setting [6:4] alc_thr2 011b set the recovery speed switch over thresh 2 06h [2:0] alc_fr2 100b recovery coefficient 2 setting 07h [2:0] alc_fr3 100b recovery coefficient 3 setting continued on next page LC07410LG no.a1345-30/36 continued from precceding page adrs bit name init description [7] alc_fullen 0b full scale dete ction mode setting. 1: on 0: off [6] alc_zcd 1b controls the gain change operation at zerocross timing. 1: on 0: off [5:4] alc_zcdtm 01b set the zerocross detection timeout time. valid when [alc_zcd] = 1. 11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs [3:2] alc_tlim 01b set the inter-zerocross attack limit. 11: 4db 10: 2db 01: 1db 00: 0.5db valid when [alc_zcd] = 1 08h [1:0] alc_rwt 10b set the recovery alert time 11: 1024/fs 10: 512/fs 01: 256/fs 00: 128/fs [7] alc_ngen 0b set the noise gate function 1: valid 0: invalid [6:4] alc_ngth 100b set the noise gat e silent detection thresh level [3:2] alc_ngdt 10b set the noise gate silent de tection time/set the gain attenuation time 09h [1:0] alc_ngrt 01b set the noise gate reset time 0bh [5:0] alc_vmax 0eh set the maximum pga gain value (init value 0eh: 0db) 0ch [5:0] alc_gain 0eh set the manual mode pga gain value (init value 0eh: 0db) [7] filter2 0b programmable filter2 setting 1: on 0: off [6] filter1 0b programmable filter1 setting 1: on 0: off [5:4] wind_cut 00b wind_cut function (hpf fc setting) 11: 400hz 10: 300hz 01: 200hz 00: off [3] ad_mute 0b adc output mute setting 1: enables mute function 0: disables mute [2] fbclk 0b set the bclk frequency 1: 32fs 0: 64fs 0dh [1:0] rec_alc pb_alc 10b set the alc mode 10: rec alc 01: pb alc 00/11: alc off [4] adf_master 0b adf circui t 1: master mode 0: slave mode [3] adf_dac_inv 0b adf circuit, dac input data setting 1: inverted 0: non-inverted [2] adf_adc_inv 0b adf circuit, adc input data setting 1: inverted 0: non-inverted 0eh [1:0] adf_mode 00b adf ci rcuit, format setting 11, 10: right-justified 01: left-justified 00: i 2 s [5] adf_lb 0b loopback setting 1: internal loopback is done 0: internal loopback is not done 0fh [1] sel_use_dsp 0b dsp route setti ng 1: pb (dac) side 0: rec(adc) side [7] evr_mute 1b controls the mute f unction of the evr (digital) circuit. 1: enables mute function. 0: disables mute function. 10h [6:0] evr_gain 00h controls the gain function of the evr (digital) circuit. 00h: -64db 57h: +12db to 2ch: -9.5db /0.5db step 2bh: -10db to 0ch: -41db /1.0db step 0bh: -42db to 00h: -64db /2.0db step [6] evr_volzcd 1b controls the gain change operation of the evr (digital) circuit at zerocross timing. 1: on 0: off [5:4] evr_zcdtm 01b set the zerocr oss detection timeout time of the evr (digital) circuit. 11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs valid when [evr_zcd] = 1 [2] evr_softsw 1b controls the soft switch f unction of the evr (digital) circuit. 1: on 0: off 11h [1:0] evr_voltm 00b set the time of th e soft switch function of the evr (digital) circuit (dos not depend on fs). 01: 2.278ms/step, (200ms: when +12db ? mute) 00: 1.142ms/step , (100ms: when +12db ? mute) 11, 10: set prohibition [7] lo_mute 1b line out circuit, mute function 1: enables mute function 0: disables mute function [6] lo_vrefsw 1b state setting when power of lineout is downed 1: connects to the reference power source (vref) 0: does not connects to the re ference power source (vref) [5:4] lo_gain 10b line out circuit, gain selection 11: +8db 10: +6db 01: +4db 00: 0db [2] sel_gain 0b selector circuit, gain selection 1: +6db 0: 0db 12h [1:0] sel_in 01b selector input selection setting 00: prohibition 01: dac 10: alc 11: prohibition [7:6] bpmode 00b beep output mode sett ing 01: ext-beep operation 00: off 11: int-beep operation/parallel control 10: int-beep operation/serial control [5:4] bpvol 11b beep gain selection 11: -21db 10: -18db 01: -15db 00: 0db [3:2] sp_idl 10b set the idling current of the speaker amplifier circuit 11: 2.0ma 10: 1.0ma 01: 0.67ma 00: 0.5ma 13h [1:0] sp_bias 00b set the bias contro l of the speaker amplifier circuit 11: 0.833 v dd a 10: 0.766 v dd a 01: 0.666 v dd a 00: 0.5 v dd a continued on next page LC07410LG no.a1345-31/36 continued from preceding page adrs bit name init description [7] sp_out_en 0b enables or disabl es the speaker amplifier circuit 1: on 0: off [6] sp_tsd_en 1b enables or disables the thermal sh utdown function of the speaker amplifier circuit 1: on 0: off [4] vd_gain 0b selects the driver gain of video circuit 0: +6db 1: +12db 14h [3:0] vd_dctl 0001b select the input sy nc level dc offset of video circuit 0000: -25mv to 1110: 325mv (+6db) 0000: -12.5mv to 1110: 162.5mv (+12db) 15h [3:0] fs 1000b sampling frequency setting 1000: 48khz / 0111: 44.1khz / 0110: 32khz / 0101: 24khz 0100: 22.05khz / 0011: 16khz / 0010: 12khz / 0001: 11.025khz/ 0000: 8khz 16h [5:4] sel_mclko 00b mclko output selection 00: ?l? 00: ?h? 01/11: mclkin [pll_pdx = 0] or pll output [pll_pdx = 1] 16h 17h [0] [7:0] pll_div1 07dh sets the basis clock frequency ratio (div1) 000h: prohibition 001h: 1/1 to 1ffh: 1/511 default: 07dh(125) 18h 19h [0] [7:0] pll_div2 080h sets the vco output frequency ratio (div2) 000h: prohibition 001h: 1/1 to 1ffh: 1/511 default: 080h(128) [5:4] pll_fcki 00b sets the mclk in input frequency ratio 00: 1/1 01: 1/2 10: 1/4 11: 1/4 1ah [1:0] pll_div3 00b sets the mclk ou tput frequency ratio (div3) 00: 1/1 01: 1/2 10: 1/4 11: 1/4 1bh [7:0] a1[15:8] 00h 1ch [7:0] a1[7:0] 00h sets the programmable filter1 coefficient a1 1dh [7:0] a2[15:8] 00h 1eh [7:0] a2[7:0] 00h sets the programmable filter1 coefficient a2 1fh [7:0] b0[15:8] 40h 20h [7:0] b0[7:0] 00h sets the programmable filter1 coefficient b0 21h [7:0] b1[15:8] 00h 22h [7:0] b1[7:0] 00h sets the programmable filter1 coefficient b1 23h [7:0] b2[15:8] 00h 24h [7:0] b2[7:0] 00h sets the programmable filter1 coefficient b2 25h [7:0] a1[15:8] 00h 26h [7:0] a1[7:0] 00h sets the programmable filter2 coefficient a1 27h [7:0] a2[15:8] 00h 28h [7:0] a2[7:0] 00h sets the programmable filter2 coefficient a2 29h [7:0] b0[15:8] 40h 2ah [7:0] b0[7:0] 00h sets the programmable filter2 coefficient b0 2bh [7:0] b1[15:8] 00h 2ch [7:0] b1[7:0] 00h sets the programmable filter2 coefficient b1 2dh [7:0] b2[15:8] 00h 2eh [7:0] b2[7:0] 00h sets the programmable filter2 coefficient b2 [7:5] bpton 010b int-beep on duty(ton) setting 2fh [4:0] bptoff 00110 b int-beep off duty(toff) setting [7] intbpst 0b int-beep starting control (at bpmode = 10 valid) [6:4] bphz 011b int-beep frequency (fsig) setting 30h [3:0] bpcnt 0110b int-beep number of cycles (nrep) setting 31h to 39h test mic = microphone amp pga = programmable gain alc = automatic level control amplifier adc = ad converter adrs = address dac = da converter init = initial value evr = electronic variable resistor nh = n denotes a hexadecimal number adf = audio data format nb = n denotes a binary number LC07410LG no.a1345-32/36 control sequence reference voltage, line out start/stop sequence vref_bias[1] 0.5 v dd a lo_pdx lo_mute t0 t1 t2 t5 t3 t3 t4 0.5 v dd a vref_bias[0] common refernce voltage vref pin line output circuit line output signal lout1 pin ? recommendation value t0 > 1ms (pull down period, at already when l out 1 pin is gnd level.) t1 > 100ms (rapid charge period, at vref pin connected capacity is 4.7 f) t2 > 300ms (l out 1 charge time) t3 > 1ms (waiting time of mute on/off) t4 > 0s t5 > 300ms (pull down period) ? it makes it to lo_vrefsw = 1 usually. ? lo_vrefsw function at power down (lo_pdx = 0) lo_vrefsw = 1: lout1 pin becomes vref level output lo_vrefsw = 0: lout1 pin becomes hi-z speaker amplifier start/stop sequence sp_pdx 0.5 v dd s t1 t2 t3 sp_out_en t2 t3 t4 speaker amplifier input signal spoutp/n pin (speaker output) ? recommendation value t1 > 5ms (speaker bias start-up time) t2 10ms (processing period when pop sound is decreased. input signal recommends mute.) t3 > 15ms t4 > 1ms ? external capacitance conne cted to spkin pin is 0.1 f ? sp_out_en must be set to 0 when power down (sp_pdx = 0) mode. LC07410LG no.a1345-33/36 digital filter adc/dac digital filters adc digtal filter frequency response ? 140 ? 120 ? 100 ? 20 ? 40 ? 60 ? 80 0 02 134 frequency ? xfs amplitude ? db dac fir filter frequency response ? 140 ? 120 ? 20 ? 40 ? 60 ? 80 ? 100 0 0 2.5 2.0 1.5 1.0 0.5 3.0 3.5 4.0 frequency ? fs gain ? db dac fir filter ripple ? 0.05 ? 0.04 0.01 0.02 0.03 0.04 0 ? 0.01 ? 0.02 ? 0.03 0.05 0 0.4 0.3 0.2 0.1 0.5 frequency ? fs gain ? db adc digtal filter frequency response (passband) ? 0.2 0 0.05 0.1 0.15 ? 0.15 ? 0.1 ? 0.05 0.2 0 0.4 0.3 0.2 0.1 0.5 frequency ? xfs amplitude ? db LC07410LG no.a1345-34/36 programmable digital filter setting example @fs = 48khz lpf ? 140 ? 120 ? 100 ? 20 ? 40 ? 60 ? 80 0 0.1 2 1 357 2 10 357 2357 100 f ? khz response ? db hpf ? 45 0 ? 40 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 5 0.01 7 0.1 5 3 27 1 5 3 27 5 3 2 10 f ? khz response ? db f0 = 16khz 2khz 8khz 4khz q = 0.7 f0 = 100hz 200hz 400hz 1khz f ? khz notch filter ? 45 ? 40 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 ? 10 ? 5 0 5 10 5 ? 20 ? 15 ? 10 ? 5 0 5 020 15 10 525 20 15 10 525 20 15 10 525 response ? db f ? khz equalizer ? 15 15 0 response ? db ? 10 ? 5 0 5 10 20 15 10 525 f ? khz equalizer ? 15 15 0 response ? db f ? khz high shelf filter ? 25 0 response ? db f0 = 8khz f0 = 5khz fb = 4khz fb = 1khz gain +12db gain -6db gain -12db gain +6db fb = 2khz fb = 8khz fb = 4khz 2khz f0 = 16khz f0 = 14khz f0 = 20khz f0 = 15khz q = 0.7 1khz 1khz 2khz fb = 4khz gain (-6db) (-20db) (-12db) f0 = 16khz fb = 12khz fb = 3khz gain +12db gain -6db gain -12db gain +6db fb = 1khz fb = 4khz f0 = 8khz LC07410LG no.a1345-35/36 checkpoints the user is responsible for ascertaining whether this ic can be adopted for the set to be mass production by the user, including the various conditio n for mounting in the set. 1) power supply ? the 3.0v type and 3.0v/5.0v type are available as the power supply pins. 1.8v type: digital power supply i/o (v dd io) 3.0v type: digital power supply (v dd ), analog power supplies (v dd r, v dd a, v dd v, v dd p) 3.0v/5.0v type: analog power supply (v dd s) ? the power-on sequence is such that the power is first app lied in sequence starting with the circuits that operate using a high voltage and the power is turned off in sequence starting with the circuits that operate using a low voltage. 2) resetting ? at power-on, the pdnb pin must be set to low without fail. (a) or (b) is executed as shown in the figure below. pdnb pdnb (a) 0.8v (b) 0.8v td td td > 1 s power pin 95% power startup level normal operation start notes: (a) is reset at the same time as the power is first applied. (b) is reset immediately after the power is first applied. the mclkin pin clock input must be provided w ithout fail during either the (a) or (b) period. 3) 3-line serial setting ? whenever 3-line serial setting is to be performed, it must be done where the mclkin input has stabilized without fail. ? if garbled data is found, restart the ic (switching the state of the pdnb pin from low to high) and perform 3-line serial setting again. LC07410LG ps no.a1345-36/36 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. application circuit example micinp micinn micpwr alcin v dd a v ss a vref lout1 lout2 spkin beep spoutn spoutp v dd s v ss s vcofil mclkin mclko bclk lrck adout dain v dd io dv dd dv ss testin vdin vdout v dd v vdref v ss v pdnb sda sck csb v dd r v ss r vreg video out video dac p/ dsp v dd p micout v dd r 3.0v v dd s v dd v dv dd v dd io 10 f 10 f 1 f 3900pf 0.068 f 3.3k 0.47 f 0.47 f 0.1 f 2.2k to 4.7k 4.7 f 10 f 10 f 1 f 75 10 f 1 f 10 f 0.01 f 10 f 0.1 f 0.1 f line out this catalog provides information as of august, 2010. specifications and information herein are subject to change without notice. |
Price & Availability of LC07410LG
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |